ASUS uses a modified American Megatrends AMIBIOS with their Rampage III Extreme board. The menu is split into: Extreme Tweaker, Main, Advanced, Power, Boot, Tools and Exit. The Main menu is where the Time, Date, Language and detected SATA drives. The Storage Configuration and System Information screens are also here.
The Advanced menu is where you have the CPU Features, the
The Extreme Tweaker is where all the tweaking and overclocking is done on the Rampage III Extreme board. CPU Level Up allows you to set your CPU to a higher setting than the default dependent on what CPU is installed on the System. Ai Overclock Tuner allows you to set the overclock settings of the CPU according to whether you want Manual, Auto, XMP, CPU Level Up and ROG Memory Profile. Here’s a chart with the various settings in the BIOS:
| Setting | Range |
| BCLK Frequency | 100-500 |
| PCIE Frequency | 100-1650 |
| DRAM Frequency | DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, DDR3-1866, DDR3 2133, DDR3-2400 |
| UCLK Frequency | 1600, 1733, 1866, 2000, 2133, 2266, 2400, 2533, 2666, 2800, 2933, 3066, 3200, 3333. 3466 |
| QPI Link Data rate | Slow Mode, 4800MT/s, 5866MT/s, 6400MT/s |
| DRAM Timing Control | |
| CAS Latency | 3 DRAM CLK, 4 DRAM Clock-10 DRAM Clock, 11 DRAM Clock |
| RAS# to CAS# | Delay 3 DRAM Clock-10 DRAM Clock |
| RAS# to PRE Time | 3 DRAM Clock-10 DRAM Clock |
| RAS# ACT Time | 3 DRAM Clock, 4 DRAM Clock-16 DRAM Clock, 17 DRAM Clock |
| RAS# to RAS# Delay | 1 DRAM Clock-7 DRAM Clock |
| REF Cycle Time | 30 DRAM Clock,36 DRAM Clock, 48 DRAM Clock, 60 DRAM Clock, 72 DRAM Clock, 82 DRAM Clock, 88 DRAM Clock, 90 DRAM Clock, 100 DRAM Clock, 110 DRAM Clock |
| WRITE Recovery Time | 1 DRAM Clock-15 DRAM Clock |
| READ to PRE Time | 3 DRAM Clcok-15 DRAM Clock |
| FOUR ACT WIN Time | 1 DRAM Clock-63 DRAM Clock |
| Back to Back CAS# | Delay 4 DRAM Clock-18 DRAM Clock |
| Timing Mode | 1N, 2N, 3N |
| Round Trip Latency on CHA 46 | Advance 15 Clock-Advance 1 Clock |
| Round Trip Latency on CHB 0 | Advance 15 Clock-Advance 1 Clock |
| Round Trip Latency on CHC 0 | Advance 15 Clock-Advance 1 Clock |
| WRITE to READ DD delay | 1 DRAM Clock-8 DRAM Clock |
| WRITE to READ DR Delay | 1 DRAM Clock-8 DRAM Clock |
| WRITE to READ SR Delay | 1 DRAM Clock-22 DRAM Clock |
| READ to WRITE DD delay | 2 DRAM Clock-14 DRAM Clock |
| READ to WRITE DR delay | 2 DRAM Clock-14 DRAM Clock |
| READ to WRITE SR delay | 2 DRAM Clock-14 DRAM Clock |
| READ to READ Delay | 2 DRAM Clock-9 DRAM Clock |
| READ to READ Delay | 2 DRAM Clock-9 DRAM Clock |
| READ to READ Delay | 4 DRAM Clock-6 DRAM Clock |
| Write to WRITE Delay | 2 DRAM Clock-9 DRAM Clock |
| Write to WRITE Delay | 2 DRAM Clock-9 DRAM Clock |
| Write to WRITE Delay | 4 DRAM Clock-6 DRAM Clock |
| CPU Differential Amplitude | 700mV 800mV 900mV 1000mV |
| CPU Clock Skew | 100-1500ps |
| IOH Clock Skew | 100-1500ps |
| Digi+PWR Mode | X-Power, T-Balanced |
| PWM Volt Control | 6V, 7V, 8V,9V, 10V |
| Loadline Calibration | 0% calibration, 50% calibration, full calibration |
| CPU PWM Frequency | 250 KHz 500KHz, 750 KHz 1000 KHz |
| CPU Voltage Control Absolute | (VID) Relative (Dynamic) |
| CPU Voltage | 0.85000V-2.30000V |
| CPU PLL Voltage | 1.51050v-2.0535v |
| QPI/DRAM Core Voltage | 1.20000v-2.50000v |
| IOH Voltage | 1.11300v-2.19950v |
| IOH PCIE Voltage | 1.51050v-2.78250v |
| DRAM Bus voltage | 1.20575v-2.50425v |
| DRAM DATA REF Voltage on CHA/B/C | -157.5mV-+200mV |
| DRAM CTR; REF Voltage on CHA/B/C | -157.5mV-+200mV
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