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OverclockingOverclocking was once a dark art, practiced by only the most hardcore of geeks; the only who were willing to modify hardware, customize their cooling and switch jumpers in hopes to squeeze a few extra MHz out of their hardware. As time has progressed, Overclocking has become more and more mainstream, to the point now where nearly every motherboard you can find out there - even the cheapest budget modes - will allow some form of Overclocking, or at least pseudooverclocking. While Overclocking is not as difficult as it once was, it still possesses some elements of risk. Hardware can die from being pushed too far with inadequate cooling. Thus, while we here at Motherboards.org love to overclock, we do not force you to follow in our footsteps, and as such any ill-effects of the experiments are your own doing. Let's get onto the methodology and the results shall we? We start off with the memory modules at their stock timings (2-2-2-5) and voltages (2.6V), on a system where the processor's multiplier has been backed and voltage increased by a healthy .15V, in order to provide headroom. We begin by moving the HTT bus (also known as FSB) up slowly, taking relatively safe 5MHz hops, and using SuperPi to test for the resulting stability. When the memory becomes unstable, thus crashing SuperPi or causing a BSOD, we take to boosting the Memory voltage - usually by .1V intervals, up to 3V in the end. When 3V has been reached, we start loosening the memory's timings by the lowest possible intervals, starting with RAS to CAS. When the benefits of this drop dry up, we take to loosening the TRAS - usually producing little change in frequency gains, but facilitating stability at higher frequencies. When the benefits (if any) of this increase are negated, we boost the CAS and RAS Precharge simultaneously, and continue to push the modules onward. At the point where these raises no longer prove beneficial, we once again loosen the timings, this time dropping CAS, RAS to CAS and RAS Precharge simultaneously, to a maximum of four. At this point, we find the module's maximum frequency, and with a voltage of 3V, we begin to run a 32M test in SuperPi, to check for stability. In the event of a crash, the memory's frequency is backed off in 5MHz intervals until stability is attained. We began the testing at the standard timings, finding a limit relatively quickly at 210MHz with the standard voltage. By raising the voltage in .1V increments, we found a fairly linear increase of 5 MHz per increment, which unfortunately ended with a 3MHz jump at 3V. At this point, we backed off the RAS to CAS timing, which bought us a respectable 10MHz leap, taking our memory to 235 MHz, as well as a platform to continue our clocking from. At first, we tried to loosen TRAS, CAS and RAS Precharge individually, and upon finding little purchase, we decided to drop all three at once. This proved to be the golden ticket to attend the next level of performance, one which topped out at a respectable 275MHz. Interestingly enough, further loosening the timings to a maximal 3-4-4-9 resulted in absolutely no frequency gain, nor stability boost for this level of frequency. Sadly, 275MHz was just stable enough to perform benchmarks on, but repeatedly failed the 32M test. As we continued to back the frequencies down, even a venerable 260MHz showed instability, leaving us at a final speed of 255MHz. While this is respectable, it is a disappointing score for modules based on Samsung's Excellent TCCD chips. Granted, DDR500 at midrange latencies is nothing to sneeze at; neither is the paramount 6.53GB/s of memory bandwidth that flowed out as a result.
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