AMD Vesus Intel Battle of the Dual-Core CPUs :: The CPUs

05-09-2005 · Category: Hardware - Processors

By Doc Overclock


Model Frequency Cache
4800+ 2.4GHz 1MB L2 cache-per-core
4600+ 2.4GHz 512KB L2 cache-per-core
4400+ 2.2GHz 1MB L2 cache-per-core
4200+ 2.2GHz 512KB L2 cache-per-core

L1 Cache Sizes: Each core has its own 64K of L1 instruction and 64K of L1 data cache (256KB total L1 per processor)

  • CPU to Memory Controller: Same as CPU core frequencies
  • Memory Controller: Shared integrated 128-bit wide memory controller
  • Types of Memory: PC1600, PC2100, PC2700 and PC3200 DDR memory
  • HyperTransport Links:1
  • HyperTransport Spec: 2GHz (2x 1000MHz / DDR)
  • Effective data bandwidth: 14.4 GB/sec [8GB/sec x1 HyperTransport link + 6.4GB/sec memory bandwidth]
  • Packaging: 939-pin organic micro-PGA
  • Fab location: AMD's Fab 30 wafer fabrication facility in Dresden, Germany
  • Process Technology: 90nm (.09-micron) Silicon on Insulator (SOI)
  • Approximate Transistor count: 233.2 million
  • Approximate Die Size: 199mm2
  • Nominal Voltage: 1.35-1.40V
  • Max Thermal Power: 110 W
  • Max Ambient Case Temp: 65 degrees Celsius
  • Max Icc (processor current): 80A

AMD Vesus Intel Battle of the Dual-Core CPUs

The new Dual-Core AMD Athlon 64 X2 series of CPUs are essentially CPUs based around the Opteron core, with the differences being in the amount of HyperTransport links that are available. The difference is, the Opteron offers two HyperTransport links, while the desktop X2 offers a single HT link to handle its I/O requests. As you can see from the chart above the new X2 offers a total bandwidth of 14.4GB/s, (6.4GB/s of peak theoretical memory bandwidth and 8GB/s of peak theoretical I/O throughput) which is way and above Intel's Dual-Core that only offers 6.4GB/s. This leaves a lot of supposed headroom for the X2 and if realized could put an even more serious dent in Intel's desktop platforms being offered currently. The chips start with the 4200+ running at 2.2GHz offering 1MB of L2 cache per core and go up to the 4800+ running at 2.4GHz and offering 1MB of L2 cache per core. The new X2 series also fully supports the 64-Bit extensions for running the latest Windows XP 64-Bit Edition.

One of the differences between AMD and Intel's approach to memory architecture is with AMD they share a memory controller on the die. With Intel's dual-core CPUs, the memory controller is off-die on the Northbridge. The new X2 series CPUs have the same design, as the new revision E chips with the addition of SSE3 instructions, which should prove to be a valuable asset to the X2 series. SSE3 is SIMD (single instruction, multiple data) instructions that allow faster processing in certain programming tasks enabling them to execute in fewer cycles with the processor. Made on the 90nm SOI (Silicon On Insulator) technology in the Dresden Germany wafer fabrication facility, and the CPU still uses the Socked 939 ZIF interface and will work in many of the current motherboards available with a simple BIOS flash. This will help in sales, as Intel's Dual-Core solution needs a completely new motherboard to support their new CPU. AMD right off the bat has will win the hearts/ dollars of many customers by these small differences, as anyone who currently owns a new AMD board can just pop in the new chip, and they have a Dual-Core system. This was a very wise move on AMD's behalf.


Model Frequency Cache
Pentium D 820 2.8 GHz (FSB800) 1MB L2 cache-per-core
Pentium D 830 3.0 GHz (FSB800) 1MB L2 cache-per-core
Pentium D 840 3.2 GHz (FSB800) 1MB L2 cache-per-core
Pentium EE 840 3.2 GHz (FSB800) 1MB L2 cache-per-core
  • Pentium EE 840
  • Package LGA775
  • Processor rating 840
  • Clock frequencies 3.20 GHz
  • Bus frequency 800 MHz
  • Core Dual Core
  • Manufacturing technology 90nm, strained silicon
  • L1 data cache 2 x 16 KB
  • Trace cache 2 x 12000 micro-ops
  • L2 cache 2 x 1024 KB
  • EM64T Yes
  • XD-bit Yes
  • EIST Yes
  • Hyper-Threading Yes
  • SIMD-instructions support SSE, SSE2, SSE3
  • Number of transistors 230 mln
  • Die size 206

AMD Vesus Intel Battle of the Dual-Core CPUs
AMD Vesus Intel Battle of the Dual-Core CPUs

Intel has taken their Prescott core and connected two of them by way of a bolted design and that is what essentially makes up the Smithfield core. Intel offers a few different versions of their Dual-Core Pentium class CPUs, starting with the D series 820 running at 2.8GHz offering 1MB of cache, but no Hyper-Threading all the way up to the Pentium EE running at 3.2GHz and offering 1MB of L2 cache on each core and includes HT technology. Intel has made some improvements in the Prescott core since its initial release to help with heat issues. With the addition of XD-Bit and C1E & TM20 and then the even further addition of EIST (Enhanced Intel Speed Step) technology, they have done a lot to improve thermal temperatures. The Extreme Edition 840 has each of the processing units having an independent 1MB L2 cache. Hyper-Threading will be enabled on both cores, giving the system a total of four processing threads available to the OS.

AMD Vesus Intel Battle of the Dual-Core CPUs

Each independent core communicates with its twin core via a special bus interface, and the cores can physically access the others L2 caches by accessing this interface, or through the front side bus. All Smithfield based products support Intel's EM64T extensions for running Win XP 64. The 820 through 840 CPUs also run at the 800MHz FSB in lieu of their higher speed single core CPUs like the 3.73GHZ EE, which has a 1066MHz FSB. Incidentally, this may cause the CPU to take a performance hit in many single threaded applications when compared to its 1066MHz brethren. One thing to note is that in order to use this CPU you must first purchase a new motherboard that supports it. With thermal problems as they are we will most likely not see Intel passing the 3.2GHz barrier with their new Dual-Core design as that would surpass the 130 W thermal envelope of Intel's 2005 platform. In the future, Intel plans to change their Dual-Core design to get the most efficiency out of their chips in lieu of just clock increases, and we will just have to see what the future holds for us when it gets here.