One major difference between the AGP/PCI bus and the PCI Express bus is that the AGP/PCI bus is based on parallel technology while the PCI Express is based off the Serial bus. The Parallel bus while being able to send multiple bits of information along its data stream is very hard put to keep data flowing in a timely fashion along all its pathways. Although the PCI Express bus only sends one bit per clock in each direction, a single PCI Express lane is designed to scale well beyond 2GHz. The standard 32bit PCI bus speed is 33MHz and the DDR memory is connected to the rest of the system in parallel and runs at a few hundred MHz.

ATI and NVIDIA both provided cards for the launch of the 925X/915 platforms and NVIDIA was especially generous in their help if albeit a bit late with their promises. NVIDIA gave us a pair of PCI Express 6800Gt cards (Thanks Brian) and an AGP 6800 Ultra for our test bench this round. ATI was rather unkind this round and could not provide a high-end card of any caliber for this round, instead sending us a mid level PCI Express X600 and its AGP counterpart the 9600XT. What's up with that anyways? The major differences between both ATI's and NVIDIA's approach to PCI Express graphics solution has been the discussion between the two companies for the past several months in an attempt to finalize a permanent standard.

NVIDIA takes an economical approach to solving the problem, they use an 8X GPU that uses an AGP-to-PCI Express bridge chip that NVIDIA calls the High Speed Interconnect (HSI). The additional bridge could offer a performance penalty especially as the PCI Express matures, but this is yet to be seen. ATI decided to skip all the BS and built new GPUs with a PCI Express x16 interface in the core that support the new 16X standard natively and this is the better if more costly solution. In the long run NVIDIA will have to adapt to this design scheme as well and they will continue to use the HSI as necessary to link back to AGP 8X standard for older platforms as they develop native 16X GPUs.