D'Arcy Lemay · 12-30-2004 · Category:
Explaining PCI Express
The grand scheme of PCI Express is to be like the One Ring in JRR Tolkien's tale, "one bus to rule them all". In the end though, "one bus" isn't a really good descriptor of how PCI Express works. "One protocol" would be a more apt way to define the goal. This is because PCI Express unlike its predecessor is not a shared bus design; instead it's what is considered a "point to point" topology. In fact, PCI Express really steals a lot from local area network (LAN) design. You can have a bunch of clients, each of whom has a direct path to a switch, which routes traffic to where they want to go. So instead of fighting for control of the whole bus, they only have their own discreet path to worry about. A router or switch sits in between the two devices trying to communicate, and does the work of sending data in between the two. To each device though there is a layer of abstraction, they aren't concerned with how it gets there, it's just like the mail analogy above.
This is how PCI Express is able to function without any changes to the operating system from PCI, all the new stuff happens below its area of interest. Similar to a LAN, data is broken up into "packets". While PCI first sends out an address, which each device listens for (their "name") then the data associated with that, a packet contains both. The "header" of the packet tells the end address, routing, flow control, and priority. That last point is important. As network schemes evolve for both LAN and wireless cell phone communication, handling streaming data which does not tolerate delays or changes in bandwidth well is becoming more and more important. This is because of video on demand, higher quality audio, and so on. These types of traffic are of course also common in the personal computer. Being able to change the priority of a task allows it to move up or down in the queue, regardless of the timestamp of when it showed up. The other part of PCI Express's similarity to a LAN is its form of communication. The old PCI bus was considered a "parallel" interface. PCI Express on the other hand is a high-speed serial design. Most current devices are moving to this, as seen by SATA, USB and so on.
Once upon a time serial was the design of choice, back when RS232 and your COM ports were actually used for something besides taking up space on the motherboard backplane. At the time, serial communication was slow, and was replaced by parallel. If you can't make a single line faster, it makes sense instead to put a bunch of them beside each other, each one passing one bit of a larger word. At the end of the line, you take all of those separate lines and combine them back into one whole. Advances in materials are one reason for why serial communication can attain much higher speeds than before, but other factors come into play as well. The method of handshaking, error detection and correction, and perhaps most importantly the increase in speed that both the sending and receiving devices can operate at PCI Express allows for a bit of both to work in concert to achieve high transmission rates. At the bare minimum there are two paths, making up a "lane". This X1 link needs both to allow for bidirectional communication, one up, and one down. Each direction can carry 250 megabytes per second, or MBps. As mentioned at the start of the article, PCI in total has a bandwidth of 133MBps for the entire bus. And that's just for an X1 link, you can also pair up PCI Express lanes creating up to an x32 monster allowing for 8GBps of bandwidth in each direction. This is how PCI Express is able to replace AGP as a communication protocol for bandwidth demanding graphics. An x16 PCI Express link is able to blow out 4GBps in each direction, for 8GBps in total.
Now, considering that in most cases even AGP 4x is capable of supplying data for graphics, the bandwidth isn't really what's important here. Instead it's two other factors, one being the ability of PCI Express to supply more power through the socket in these days of graphics cards drawing equivalent power to a CPU. The other factor is the use of multiple graphics cards again, much like in the days of 3dfx. Because of the design of PCI Express and it's ability to negotiate lane width you can take one x16 slot, and split it instead into two x8 ones. This still provides more than enough bandwidth for each card by itself, while allowing them to communicate with the switch and the rest of the system. I'm not sold on the technology yet due to the cost of buying and powering two high-end graphics cards, but the technical capabilities are incredible.
- History of PCI
- Explaining PCI Express